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STV8130AD
ADJUSTABLE AND +3.3 V DUAL VOLTAGE REGULATOR WITH DISABLE AND RESET FUNCTIONS
PRELIMINARY DATA
FEATURES
s Input Voltage Range: 5 V to 18 V s Output Currents up to 750 mA s Fixed Precision Output 1 Voltage: 3.3 V 2% s Adjustable Output 2 Voltage: 2.8 to 16 V s Output 1 with Reset Function s Output 2 with Disable Function by TTL Input s Short-circuit Protection at both Outputs s Thermal Protection s Low Dropout Voltage SIP9 (Plastic Package) ORDER CODE: STV8130A#
DESCRIPTION
The STV8130A# and STV8130D# are monolithic dual positive voltage regulators designed to provide a fixed precision output voltage of 3.3 V and an adjustable voltage between 2.8 and 16 V for currents up to 750 mA. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. Output 2 can be disabled via the TTL input. Short-circuit and thermal protections are included. DIP16 (8 + 8) ORDER CODE: STV8130D#
9 8 7 6 5 4 3 2 1
Tab is connected to GROUND
INPUT1 OUTPUT1 OUTPUT2 INPUT2 PROGRAM DELAY CAPACITOR RESET DISABLE GROUND DISABLE RESET DELAY CAPACITOR PROGRAM INPUT2 OUTPUT2 INPUT1 OUTPUT1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND
September 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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STV8130AD
TABLE OF CONTENTS
Chapter 1 Chapter 2
2.1 2.2 2.3
GENERAL INFORMATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Absolute Maximum Ratings ................................................................................................ 4 Thermal Data ...................................................................................................................... 4 Electrical Characteristics ...................................................................................................... 4
Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 APPLICATION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
POWER DISSIPATION AND LAYOUT INDICATIONS . . . . . . . . . . . . . . . . . . . . . .8 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
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STV8130AD
GENERAL INFORMATION
1
GENERAL INFORMATION
Figure 1: STV8130A# Block Diagram
DELAY CAPACITOR 3 6 Reference RESET
INPUT1
1
Regulator 1 Protection
9
OUTPUT1
INPUT2
2
Regulator 2
8
OUTPUT2
DISABLE
4
7 PROGRAM 5 GROUND
Figure 2: STV8130D# Block Diagram
DELAY CAPACITOR 3 5 Reference RESET
INPUT1
1
Regulator 1 Protection
8
OUTPUT1
INPUT2
2
Regulator 2
7
OUTPUT2
DISABLE
4
6 PROGRAM
Pins 9 to 16 GROUND
3/12
ELECTRICAL CHARACTERISTICS
STV8130AD
2
2.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
DC Input Voltage at pins INPUT1 and INPUT2 Disable Input Voltage at pin DISABLE Output Voltage at pin RESET Output Currents Power Dissipation Storage Temperature Junction Temperature
Symbol
VIN VDIS VRST IOUT1,2 Pt TSTG TJ
Value
20 20 20 Internally Limited Internally Limited -65 to +150 0 to +150
Unit
V V V
C C
2.2
Thermal Data
Parameter
Thermal Resistance (Junction-to-Case) Thermal Resistance 1 (Junction-to-Ambient) Maximum Recommended Junction Temperature Operating Free Air Temperature Range STV8130A# STV8130D# STV8130A# STV8130D#
Symbol
RthJC
Value
9 15 50 56 140 0 to +70
Unit
C/W
RthJA TJ TOPER
C/W C C
1. Mounted on board. For more information, refer to Section 5.
2.3
Electrical Characteristics
TAMB = 25 C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified.
Symbol
VOUT1 VOUT2 VIO1,2
Parameter
Output Voltage Output Voltage Dropout Voltage
Test Conditions
IOUT1 = 10 mA IOUT2 = 10 mA IOUT1,2 = 750 mA 6 V < VIN1 < 12 V 12 V < VIN2 < 18 V IOUT1,2 = 200 mA 5 mA < IOUT1 < 600 mA 5 mA < IOUT2 < 600 mA
Min.
3.23 2.8
Typ.
3.30
Max.
3.37 16.0 1.4 50 100
Unit
V V V
VO1,2LI
Line Regulation
mV
VO1,2LO
Load Regulation
100 200
mV
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STV8130AD
Symbol
IQ VO1RST VRTH tRD VRL IRH
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
IOUT1 = 10 mA, OUTPUT2 Disabled K = VOUT1, IOUT1 50 mA See circuit description. Ce = 100 nF See circuit description. K - 0.4 20 K - 0.25 50 25 0.4 10
Min.
Typ.
Max.
2 K - 0.1 75
Unit
mA V mV ms V A
Quiescent Current Reset Threshold Voltage1 Reset Threshold Hysteresis Reset Pulse Delay
Saturation Voltage in Reset Condition IRESET = 5 mA Leakage Current in Normal Condition VRESET = 10 V V 0 10 6 K 0 = -----------------------T V 0 TJ = 0 to + 125C
KOUT1, 2
Output Voltage Thermal Drift
100
ppm/C
IOUT1,2SC Short Circuit Output Current VDISH VDISL IDIS VREF TJSD
VIN1 = 7 V, VIN2 = 10 V VIN1,2 = 16 V2 2
1.6 1.0
A V
Disable Voltage when pin DISABLE is High (OUTPUT2 active) Disable Voltage when pin DISABLE is Low (OUTPUT2 disabled) Disable Bias Current Reference Voltage at PROGRAM Pin Junction Temperature for Thermal Shutdown 0 V < VDIS < 7 V
0.8 -100 2.44 145 2
V A V C
1. This reset signal is activated by a decrease of VOUT1 voltage which can be due to an overload of pin OUT1 or by a lack of Input Voltage (VIN1). 2. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is only guaranteed for input voltages up to 16 V.
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CIRCUIT DESCRIPTION
STV8130AD
3
CIRCUIT DESCRIPTION
The STV8130A# and STV8130D# are dual-voltage regulators with Reset and Disable functions. The two regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second regulator will not work if pin INPUT1 is not supplied. The adjustable voltage of pin OUTPUT2 (VOUT2) is defined by output bridge resistors (R1, R2): the values of these resistors are calculated to obtain, with the targetted value for VOUT2, the reference voltage (VREF = 2.44 V) on the median point connected to pin PROGRAM. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.2 V. The Disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin DISABLE. The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1 - 0.25 V (3.05 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. This drop can be caused by a parasitic loading condition on pin OUTPUT1 or by a too low value of VIN (short powering off). When the voltage at pin OUTPUT1 exceeds VOUT1 - 0.2 V (3.1 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.44 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 4.
C e x 2.44V t RD = ---------------------------10A
Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.84 V).
Figure 3: Reset Diagram
10 A VREF OUTPUT1 REG VREF = 2.44 V +a - 50 3 Ce VREF 0.6V + b RESET
Figure 4: Internal Reset Voltages VOUT1 K VO1RST
VRTH
RESET K = Actual Value of VOUT1
Power On tRD
tRD
Power Off
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STV8130AD
APPLICATION DIAGRAMS
4
APPLICATION DIAGRAMS
Figure 5: STV8130A# Typical Application
RESET Ce 6 RESET V IN1 1 INPUT1 0.1 F
R 1 + R2 V O2 = V R EF -------------------R1
3 DELAY CAPACITOR OUTPUT1 9
R1 Value (typ.) = 10 k
V OUT1
VREF = 2.44 V
STV8130A#
V IN2 2 INPUT2 GROUND 5 C1 C2 DISABLE 4 OUTPUT2 8 PROGRAM 7 C3 C4 R2 V OUT2
DISABLE
R1
C1 to C4 = 10 F
Figure 6: STV8130D# Typical Application
RESET Ce 5 RESET V IN1 1 INPUT1 0.1 F
R 1 + R2 V O2 = V R EF -------------------R1
3 DELAY CAPACITOR OUTPUT1 8
R1 Value (typ.) = 10 k
V OUT1
VREF = 2.44 V
STV8130D#
V IN2 2 INPUT2 GROUND C1 C2 Pins 9 to 16 DISABLE 4 OUTPUT2 7 PROGRAM 6 C3 C4 R2 V OUT2
DISABLE
R1
C1 to C4 = 10 F
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POWER DISSIPATION AND LAYOUT INDICATIONS
STV8130AD
5
POWER DISSIPATION AND LAYOUT INDICATIONS
The power is mainly dissipated by the two device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming:
q q
Maximum Ambient Temperature = 70 C Maximum Junction Temperature = 140 C
Device
STV8130A# Yes No STV8130D# Yes 32 2.2 20 56 to 40 3.5 1.25 to 1.75
Heat Sink
No
RthJA in C/W
50
PMAX in W
1.4
Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP16 Package without Heat Sink
60 RthJA C/W 55 50 45 40
To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. Test Board with "On Board" square heat sink area.
6 0 2 4 8 10 12 Copper area (cm) (35 m plus solder) Board is face-down
Figure 8: Metal plate mounted near the STV8130D# for heat sinking
Top View Bottom View
8/12
STV8130AD
PACKAGE MECHANICAL DATA
6
PACKAGE MECHANICAL DATA
Figure 9: 9-Pin Plastic Single In Line Package
mm Dim. Min.
A a1 B b1 b3 C c1 c2 D d1 e e3 L L1 L2 L3 M N 3.2 1 3.1 3 17.6 0.25 14.5 2.54 20.32 1.122 0.85 3.3 0.43 1.32 21.2 0.5 1.6 0.033 2.7
Inches Max.
7.1 3 24.8 0.020 0.063 0.130 0.017 0.052 0.835 0.571 0.100 0.800 0.116 0.693 0.010 0.126 0.039 0.106
Typ.
Min.
Typ.
Max.
0.280 0.118 0.976
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PACKAGE MECHANICAL DATA
Figure 10: 16-Pin Plastic Dual In-Line Package, 300-mil Width
STV8130AD
mm Dim. Min.
A A1 A2 b b2 c D e E1 L 6.10 2.92 0.20 18.67 0.38 2.92 0.36 1.52 0.25 19.18 2.54 6.35 3.30 7.11 3.81 0.240 0.115 3.30 4.95 0.56 1.78 0.36 19.69 0.008 0.735
Inches Max.
5.33 0.015 0.115 0.014 0.060 0.010 0.755 0.100 0.250 0.130 0.280 0.150 0.130 0.195 0.022 0.070 0.014 0.775
Typ.
Min.
Typ.
Max.
0.210
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STV8130AD
REVISION HISTORY
7
REVISION HISTORY
Main Changes
General Update; DISABLE pin renamed DISABLE (function remains unchanged). Thermal Data updated. Addition of DIP16 package. Thermal Data updated. Figure 1 and Figure 2 updated. Order code changed from STV8130A and STV8130D to STV8130A# and STV8130D#. Update of VO1RST values in Chapter 2.3: Electrical Characteristics on page 4.
Revision
1.8 1.9 2.0 2.1
Date
August 2001 September 2001 September 2001 October 2001
2.2
31 January 2002
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STV8130AD
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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